ADZS-21469-EZLITE【PDF 20/62 页】KIT EVAL EZ LITE ADSP-21469

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ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469

Preliminary Technical Data

MAXIMUM POWER DISSIPATION

See Engineer-to-Engineer Note “Estimating Power Dissipation

for ADSP-2146x SHARC Processors” for detailed thermal and

power information regarding maximum power dissipation. For

information on package thermal specifications, see Thermal

Characteristics on Page 53 .

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in Table 11 may cause perma-

nent damage to the device. These are stress ratings only;

functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

Table 11. Absolute Maximum Ratings

Figure 3 shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with

external oscillator or crystal. Note that more ratios are possible

and can be set through software using the power management

control register (PMCTL). For more information, see the

ADSP-2136x SHARC Processor Programming Reference .

The processor’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL).

This PLL-based clocking minimizes the skew between the sys-

tem clock (CLKIN) signal and the processor’s internal clock.

Core clock frequency can be calculated as:

f CCLK = (2 × PLLM × f INPUT ) ÷ (2 × PLLN)

Note that in the user application, the PLL multiplier value

should be selected in such a way that the VCO frequency falls in

between 160 MHz and 800 MHz. The VCO frequency is calcu-

lated as follows:

Parameter

Internal (Core) Supply Voltage

(V DD_INT )

Analog (PLL) Supply Voltage (V DD_A )

External (I/O) Supply Voltage (V DD_EXT )

DDR2 Controller Supply Voltage

(V DD_DDR2)

DDR2 Input Voltage

Input Voltage

Output Voltage Swing

Load Capacitance

Storage Temperature Range

Junction Temperature under Bias

Rating

–0.3 V to +1.32V

–0.3 V to +1.15V

–0.3 V to +4.6V

–0.3 V to +2.7V

–0.5 V to +2.7V

–0.5 V to +3.8V

–0.5 V to V DD_EXT +0.5V

200 pF

–65 ° C to +150 ° C

125 ° C

f VCO = 2 × PLLM × f INPUT

where:

f VCO is the VCO frequency

PLLM is the multiplier value programmed

f INPUT is the input frequency to the PLL in MHz.

f INPUT = CLKIN when the input divider is disabled

f INPUT = CLKIN ÷ 2 when the input divider is enabled

Note the definitions of various clock periods shown in Table 13

which are a function of CLKIN and the appropriate ratio con-

trol shown in Table 12 .

Table 12. CLKOUT and CCLK Clock Generation Operation

Timing

ESD SENSITIVITY

Requirements

CLKIN

CCLK

Description

Input Clock

Core Clock

Calculation

1/t CK

1/t CCLK

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

Table 13. Clock Periods

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

TIMING SPECIFICATIONS

The ADSP-2146x’s internal clock (a multiple of CLKIN) pro-

Timing

Requirements

t CK

t CCLK

t PCLK

t SCLK

t DDR2_CLK

Description 1

CLKIN Clock Period

(Processor) Core Clock Period

(Peripheral) Clock Period = 2 × t CCLK

Serial Port Clock Period = (t PCLK ) × SR

DDR2 DRAM Clock Period = (t CCLK ) × SDR

vides the clock signal for timing internal memory, processor

core, and serial ports. During reset, program the ratio between

the processor’s internal clock frequency and external (CLKIN)

clock frequency with the CLKCFG1–0 pins (see Table 10 on

Page 17 ). To determine switching frequencies for the serial

ports, divide down the internal clock, using the programmable

divider control of each port (DIVx for the serial ports).

1

t SPICLK SPI Clock Period = (t PCLLK ) × SPIR

where:

SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV

bits in DIVx register)

SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register

setting)

SDR=DDR2 DRAM-to-Core Clock Ratio (Values determined by bits 20-18 of

the PMCTL register)

Rev. PrC

| Page 20 of 62 | January 2009

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